In Orthogonal Frequency Division Multiplexing (OFDM), various methods are known and used for performing a synchronization of a signal with a known sequence.
For packet transmission, such as in wireless LAN IEEE 802.11 systems or broadband wireless access IEEE 802.16a systems, an efficient method involves transmitting particular OFDM symbols which are known to a receiver.
Now referring to FIG. 1, there is shown an embodiment of a prior art synchronizer. The synchronizer performs a synchronization of an incoming series of complex samples of an incoming signal with a known sequence of a plurality of coefficients Co . . . Cn which represent a pattern within the incoming signal, known to the synchronizer.
The prior art synchronizer comprises a plurality of delay units 10, a plurality of multipliers 12, an adding unit 14 and a maximum finding unit 16.
Each delay unit 10 of the plurality of delay units 10 delays a corresponding incoming series of complex samples of the incoming signal by a fixed delay.
Each multiplier 12 of the plurality of multipliers 12 multiplies a corresponding signal with a corresponding coefficient of the sequence of the plurality of coefficients to provide a corresponding multiplied signal.
The adding unit 14 receives each of the multiplied signals and provides an added signal which is equal to the sum of each of the multiplied signals.
The maximum finding unit 16 receives the added signal and provides a synchronization signal when the added signal satisfies criteria for identifying a maximum.
Someone skilled in the art will appreciate that the maximum value signal is outputted in the case where the incoming input signal matches the sequence of the plurality of coefficients.
Unfortunately, as will be appreciated by someone skilled in the art, such embodiments may be dependent on various parameters which may affect ultimately the maximum value signal provided by the maximum finding unit 16. For instance, the signal may be affected by noise or the amplitude of the signal may be attenuated.
It will also be appreciated by the skilled addressee that a multiplier of the plurality of multipliers 12 is costly to implement in hardware, especially in the case of a Field Programmable Gate Array (FPGA) or in the case of an Application Specific Integrated Circuit (ASIC).
In view of the above, there is a need for a method and apparatus that will overcome the above-identified drawbacks and that will further be less complex to implement.